1. Field of the Invention
The present invention relates generally to the field of time division multiplexing, and specifically to the field of switching in computer networks.
2. Description of the Background Art
In the available art related to time division multiplexing and network switching, network operations are done synchronously to minimize errors. Digital switching equipment included in the networks needs to be synchronized to a single network clocking or synchronization source even if such synchronization is not required for the switching equipment's internal operations. The common system clock source is normally phase-locked to a synchronization reference signal within the network using a commonly understood phase-locked loop.
The synchronization reference signals are usually originated by a Primary Reference Source (PRS) of the network, or derived therefrom. The synchronization reference signals often take the form of regular data carrying network signals. Since such signals usually carry the data streams grouped in blocks or frames, they have to contain information about the block or frame boundaries. It is the timing of the framing information that is used as the reference for network synchronization. The typical rate of such a reference signal is 8 kHz. The system clock is usually generated by a controlled frequency oscillator running at an average frequency, the frequency being a predetermined multiple of the reference signal rate. The frequency of the oscillator is controlled by a phase-locked loop, which is required to maintain a constant timing relationship between the phase of the system clock and a long-time average phase of the synchronization reference signal.
An available system clock oscillator is implemented by using a voltage controlled oscillator (VCO), which changes its frequency in response to changes in voltage. To facilitate measurement of the current timing (phase) relationship between the system clock and the synchronization reference signal, the system clock needs to be brought to the common form of all references. This is typically done by dividing the frequency of the system clock by a fixed frequency divider.
The phase-locked loop uses a phase difference detector to measure the current timing (phase) relationship between the synchronization reference and the feedback signal derived from the system clock. From the measured phase difference, a specially chosen filter produces a signal controlling the system clock oscillator in a manner making the long-term average of the measured phase difference a constant value. The quantity of this average phase difference is typically irrelevant as long as it is constant. It is characteristic of the particular phase-locked loop design.
Available network synchronization phase-locked loops are often required to maintain only a very long-term (average) phase relationship between the reference and feedback signals. Short-term changes are ignored in order to minimize transfer of wander and jitter from the reference signal to the system clock. This is accomplished by designing, typically, a second order phase-locked loop with a transfer function bandwidth on the order of 0.1 Hz or less. An analog filter needed for such a loop would require using components having large values and size, which would make the system clock phase highly dependent on the system temperature. Therefore, such a phase-locked loop filter is typically implemented in the digital domain. Since such a filter operates at a relatively low frequency, it is feasible to implement its function as one of the procedures of an embedded real-time program executed by a microcontroller or similar integrated circuit. In particular, the same microcontroller that performs general Function Control may also be used for network synchronization.
The parameters of the filter can be controlled by the Function Control block in order to shorten the phase-lock acquisition time by temporarily widening the loop bandwidth. In a general case, the synchronization reference signals may differ among themselves in phase and/or frequency. Since the phase-locked loop is required to always bring the long-term average reference-to-feedback phase difference to a constant value, selecting a new reference, even one with an identical frequency, but a substantially different phase, results in a transition, forcing the system clock oscillator to an undesired frequency and causing a drift of the feedback signal with respect to the reference until their relative phase is brought back to the constant value.
From time to time, all of the external reference signals may be temporarily and simultaneously unsuitable for network synchronization purposes, but it may be desirable to continue running the system clock with the frequency and phase acquired before the simultaneous dysfunction occurred. In such case, the network synchronization card typically freezes the value controlling the system clock oscillator at the previously acquired level, allowing it to run free and assuming that its stability guarantees the continuation of the frequency and phase for time intervals that may be as long as 24 hours. This mode of operation of the network synchronization card is commonly referred to as a holdover mode.
In one available network synchronization card design, the mid-range frequency of such a voltage controlled oscillator is 19.44 MHz, i.e. it is 2430 times the typical 8 kHz reference frequency. The tuning range of the oscillator, relative to its center frequency, is typically on the order of +/-30 parts per million (PPM). The commonly required stability of the oscillator in the holdover mode is +/-4.6 PPM.
The requirement of high stability in holdover mode(+/-4.6 PPM) is difficult to satisfy by a controlled-frequency oscillator which, at the same time, is also required to be tuned over a relatively wide frequency range (+/-30 PPM). Oscillators that satisfy both requirements are expensive. There is therefore a need in the art for an efficient solution to this challenge.